1. Field of the Invention
The present invention relates to a method for calibrating a semiconductor device tester, and in particular to a method for calibrating a semiconductor device tester wherein a timing is calibrated using a programmable delay device so as to remove a timing difference between channels and a linearity of the programmable delay device is compensated so as to facilitate an adjustment of the timing.
2. Description of Prior Art
A semiconductor device tester includes a driver for applying a test signal to a DUT (Device under Test) and a comparator for determining a logic of a signal, which corresponds to the test signal, being outputted from the DUT. The driver carries out an output operation of a signal synchronized to an input clock signal. The comparator carries out a comparison operation of a signal synchronized to an input strobe signal.
However, in an initial state of the semiconductor device tester, a timing at which the output signal is outputted from the driver or a comparison timing by the comparator deviates from an expected timing since a difference in a time length of a signal path for each of input/output pins. Therefore, a timing calibration is required prior to carrying out various tests for the DUT.
FIG. 1 is a diagram illustrating a conventional configuration for carrying out a timing calibration of a semiconductor device tester.
Referring to FIG. 1, a main body 90 of the semiconductor device tester is connected to a socket board 94 via a dedicated cable 93. For instance, when various tests for a DUT having a BGA (Ball Grid Array) type package, the socket board 94 having a plurality of pogo pins on a surface thereof is used. A test board 96 is used to facilitate a contact of a probe 99 of a driver/comparator 98 to the plurality of pogo pins installed on the surface of the socket board 94 wherein pads installed on a front and back sides thereof are electrically connected.
FIG. 2 is a diagram illustrating an electrical layout of the conventional configuration of FIG. 1.
Referring to FIG. 2, the main body 90 of the semiconductor device tester includes a plurality of pairs of the driver and the comparator. Each pair of the driver and the comparator is connected to a common device socket terminal through a performance board 92 and the socket board 94.
FIG. 3 is a diagram schematically illustrating a conventional timing calibration.
As shown in FIG. 3, in the initial state of the semiconductor device tester, skews of clock signals CLK1 through CLKn being respectively inputted to a plurality of drivers DR1 through DRn and a plurality of comparators CP1 through CPn are inconsistent. Therefore, the inconsistency of the skew is required to be removed.
Moreover, since a round trip delay time required for a signal applied to the semiconductor device tester to return via a signal path exists, the round trip delay time should be reflected when writing a test program.